Special Reports

How Advanced Packaging Is Reshaping Inspection

By: Gregory Haley

Next-generation optical inspection is about more than just sensitivity. It’s about reliably seeing through complexity.
Novel Assembly Approaches For 3D Device Stacks

By: Laura Peters

ECTC progress report on enabling technologies, including cooling chiplets, 1µm hybrid bonding, RDL buildups, and co-packaged optics.
EDA’s Top Execs Map Out An AI-Driven Future

By: Ed Sperling

AI is accelerating the need for 3D-ICs and digital twins, and causing lots of disruption along the way.

 more »

Top Stories

Easing The Stress For Package-Level Burn-In

Employing more stress testing at the wafer level improves quality while reducing burn-i...

Detecting Slips, Scratches, And Cracks In Wafers Becoming Harder

Finding skinny defects requires a range of wavelengths.

AI Pushes High-End Mobile From SoCs To Multi-Die

Smart phone architectures look very different at the high end versus midrange and low-e...

AI: A New Tool For Hackers, And For Preventing Attacks

Experts At The Table: From jail breaking an AI to security and integrity of AI training...

6G Rollout Will Be A Patchwork At First

Spectrum allocation, infrastructure development, and varying use cases will affect when...

Mixed Messages Complicate Mixed-Signal

Analog and mixed signal content is adding risk to ASIC designs. Pessimists see the prob...

Distributing Intelligence Inside Multi-Die Assemblies

Disaggregration requires traffic cops and in-chip monitors to function as expected over...

Security Vulnerabilities Difficult To Detect In Verification Flow

New tools and techniques are being developed and can help keep the verification process...

Disruptive Changes Ahead For Photomasks?

Evolving lithography demands are challenging mask writing technology, and the shift to ...

Power Delivery Challenges For AI Chips

Rising power densities and new architectures are forcing a rethinking of interconnects,...

Physics Limits Interposer Line Lengths

Thin lines and limited ground planes keep RDL interconnects short.

Are Larger Reticle Sizes On The Horizon?

The stitching process for 1nm litho faces yield challenges with high-NA EUV.

more top stories »

Latest News

Chip Industry Week In Review

SIA's state of the industry report; TSMC's liquid cooling; copper supply risks; EU's new GenAI rules; GF acquires MIPS; LPDDR6 standard; memory market reports; GP...

Chip Industry Week in Review

U.S. lifts EDA export restrictions to China; collusion risk in the IC supply chain; Onto buys materials analysis biz; Tenstorrent acquires Blue Cheetah; assembly-...

more news »



Opinion

Iteration And Hallucination

For many aspects of an EDA flow, hallucinations from AI are no...

TSMC: King Of Data Center AI

Opinion: The foundry makes all of the logic chips critical for...

more opinions »



Research

Chip Industry Technical Paper Roundup: July 7

2.5D multi foundry chiplet solution; in-memory computation of ...

Research Bits: July 7

Memory: 3D NAND PUF; ternary alloy for NVM; quantum RAM with p...

Chip Industry Technical Paper Roundup: July 1

Integrated phononic waveguide on thin-film lithium niobate on ...

more research »



Startup Corner

EDA Startups At DAC 2025

New challenges and opportunities, many involving AI, spur the ...

Baya Systems: Moving Data Faster

Taking aim at AI bottlenecks based on NoC technology developed...

more startups »

Videos

Rethinking Scan Chains In Semiconductor Test


LLMs On The Edge


Agentic AI In Chip Design


Big Changes In Medical Electronics


Knowledge Centers / Entities, people and technologies explored